As the semiconductor industry introduces new generations of integrated circuits (IC's) having higher performance and greater functionality, the density of the elements that form the integrated circuits is increased, and the dimensions, sizes and spacings between the individual components or elements are reduced. While in the past such reductions were limited only by the ability to define the structures photo-lithographically, device geometries having even smaller dimensions created new limiting factors. For example, for any two adjacent conductive paths, as the distance between the conductors decreases, the resulting capacitance (a function of the dielectric constant (k value) of the insulating material divided by the distance between conductive paths) increases. This increased capacitance results in increased capacitive coupling between the conductors, increased power consumption, and an increase in the resistive-capacitive (RC) time constant. Therefore, continual improvement in semiconductor IC performance and functionality is dependent upon developing materials that form a dielectric film with a lower dielectric constant (k) than that of the most commonly used material, silicon oxide, in order to reduce capacitance.
New materials with extra low-k (ELK) dielectric constants and ultra low-k (XLK) dielectric materials are being investigated for use as insulators in semiconductor chip designs. A low dielectric constant material helps to enable further reductions in the integrated circuit feature dimensions. In conventional IC processing, silicon oxide was used as a basis for the dielectric material, resulting in a dielectric constant of about 3.9. Advanced low-k dielectric materials have dielectric constants below about 2.5, and may even be below about 2.0.
The substance with the lowest dielectric constant is air (with a k value of 1.0). Therefore, porous dielectrics are very promising candidates, since they have the potential to provide very low dielectric constants. However, porous films are mechanically weak by nature, and weak films may fail in the chemical mechanical polishing (CMP) processes employed to planarize the wafer surface during chip manufacturing. Further, the weak low-k dielectric materials cause difficulties in the packaging processes. For example, in wire-bonding processes, the force applied for detaching wires also causes the low-k dielectric materials underlying the bond pads to peel off.
With the use of dielectric constants having increasingly smaller dielectric constants, the dielectric peel-off becomes a significant factor affecting the yield of manufacturing of the integrated circuits, new methods are thus needed to improve the yield without affecting the electrical performance of integrated circuits.